In fabricating microelectronic semiconductor device components and the like on a semiconductor wafer (substrate or chip), e.g., of silicon, to form an integrated circuit (IC), etc., various metal layers and insulation layers are provided in selective sequence on the wafer. To maximize device component integration in the available wafer area to fit more components in the same area, increased IC miniaturization is utilized. Reduced pitch dimensions are used for denser packing of components per very large scale integration (VLSI) technique, e.g., at sub-micron dimensions, i.e., below 1 micron or 1,000 nanometers (nm) or 10,000 angstroms (A).
An ordinary electrical fuse is an expendable overcurrent protective device having a circuit-opening fusible (meltable), electrically conductive, e.g., metal or metallic material, fuse segment (fuse link) heated and destroyed by passing an overcurrent through it, so as to change it from an electrically conductive or “on” state to an electrically non-conductive or “off” state. The overcurrent heats the fuse link beyond the normal level of radiation loss of the generated resistance heat that keeps its temperature below that at which it melts. The fuse link resistance is determined by the material of which it is made, its cross sectional area and its temperature.
On the other hand, an antifuse is an electrically programmable two-electrode device of small area on a semiconductor wafer, functioning as an electronic switch, and having a fuse element of fusible insulation, e.g., dielectric, material, such as silicon dioxide, silicon nitride, or the like, of selective thickness, interposed between the two electrically conductive, e.g., metal or metallic, electrodes, i.e., an electrode and counter electrode. Upon activation by applying a programming voltage across the electrode and counter electrode to break down (cause a short in) the fusible insulation material and electrically interconnect the two electrodes, the antifuse irreversibly (permanently) changes from a high resistance, electrically non-conductive, unblown or “off”, state to a low resistance, electrically conductive, blown or “on”, state.
Antifuses are used as programmable switches to configure the circuitry of a semiconductor device. They can potentially increase wafer yield by module repair of extant circuit components in the produced semiconductor device, and thus can reduce wafer cost.
Antifuses are of various types, depending on the desired parameters, e.g., specific characteristics, and include gate oxide transistor structure based antifuses (gate oxide antifuses), dual damascene, i.e., contact, structure based antifuses (contact antifuses), bipolar junction transistor structure based antifuses (bipolar junction antifuses), and the like.
However, it is usually unclear during semiconductor wafer manufacture as to which type of electrical antifuses will exhibit sufficient desired parameters to be included in a given product. Therefore, it is generally sought to provide different antifuse types on a wafer in order to reduce the risk of inapplicability of a single antifuse type. Unfortunately, use of a combination of different antifuse types on the wafer normally leads to a wafer size overhead, i.e., a loss of tight pitch efficiency and of minimal wafer area usage.
A gate oxide antifuse is akin to a gate oxide transistor, e.g., a metal oxide semiconductor transistor (MOS transistor), and includes a gate electrode connected to a fusible insulator (fuse element), e.g., a gate oxide fusible insulator, having a source region and a drain region correspondingly laterally adjacent thereto, i.e., bilaterally having one such region on each side thereof, the source and drain regions in turn being connected to the opposing electrode.
A dual damascene antifuse is a contact antifuse (formed of a pair of standard contacts, with a fusible insulator, i.e., fuse element, therebetween), e.g., an antifuse in a via between a lower metal layer and an upper metal layer, having a conductive contact interposed between one of the electrodes and the fusible insulator (fuse element), the fuse element in turn being connected to the opposing electrode as the other contact.
A bipolar junction antifuse is akin to a bipolar junction transistor (BJT) and includes an emitter region as one electrode connected to a fusible insulator (fuse element) which in turn is connected to the opposing electrode.
Redundancy techniques are used in semiconductor device fabrication to provide deliberate duplication of circuit components to decrease the probability of a circuit failure and thus increase circuit reliability, and also to permit specific or custom design features to be incorporated selectively in the circuitry. To offset defects that can occur in the circuitry, multiple copies of a given circuit component are connected in parallel to achieve continued operation upon failure of a particular component (module repair). Also, multiple copies of a given circuit component are included to provide selective modification of the chip circuitry (custom design).
Each such multiple component is provided with an antifuse that can be blown, i.e., activated, to replace a failed component by a duplicate one during antifusing operation of redundancy activation wiring, e.g., at final IC wafer testing, or to create a custom design type circuit. Alternatively, each such multiple component is provided with an ordinary fuse for the same purpose.
High density DRAMs (dynamic random access memories) are commonly designed with memory cell redundancy whereby the redundant memory cells avoid loss of an entire memory in the event that a minor number of memory cells fail to function. Redundant memory cell activation is effected by activating antifuses (or fuses) selectively placed throughout the memory.
Some examples of the fabrication of semiconductor devices with antifuse arrangements are shown in the following prior art.
[1] U.S. Pat. No. 4,635,345 (Hankins et al.), issued Jan. 13, 1987, discloses a vertical (three-dimensional), as opposed to horizontal (two-dimensional), bipolar junction transistor (BJT) structure based antifuse in an IC memory array to increase the component density on a substrate in a semiconductor device. A thin oxide fusible element (insulator portion) is provided between the emitter region of a bipolar transistor, which emitter forms a bottom electrode (bottom terminal), and a top electrode (top terminal), e.g., of aluminum. Applying a voltage, e.g., of 12–14 volts, between the top electrode and emitter blows (activates) the thin oxide antifuse, causing the top electrode to come into contact with the emitter, to change the antifuse from electrically non-conductive or “off” state to electrically conductive or “on” state. This reference does not teach an arrangement of antifuses in vertically stacked relation and sharing a common intermediate electrode therebetween in the manner of the present invention.
[2] U.S. Pat. No. 5,436,496 (Jerome et al.), issued Jul. 25, 1995, discloses a vertical BJT structure based antifuse in an IC to increase the substrate component density in a semiconductor device. Each antifuse is selectively permanently programmable after fabrication and the antifuse structure includes a buried collector, an overlying base and an emitter above the base and having a metal contact, e.g., of aluminum, at its upper surface. Heating the metal contact/emitter interface to its eutectic melting point by a current or voltage pulse causes the aluminum to short through the emitter to the base, thereby programming the antifuse. The vertical antifuse functionally changes from a floating base transistor to a diode. This reference does not teach an arrangement of antifuses in vertically stacked relation and sharing a common intermediate electrode therebetween in the manner of the present invention.
[3] U.S. Pat. No. 5,313,424 (Adams et al.), issued May 17, 1994, discloses a semiconductor substrate having an electrically blown fuse circuit based on antifuse technology. A resistance decrease, e.g., of only 50%, due to dopant redistribution, is exhibited on blowing (activating) a given fuse. A redundancy system includes circuits to test a memory array to locate a faulty element therein, a resistor to store an address of the faulty element and electrical antifuses blown in response to binary digits of the address stored in the register on applying an enable signal from a single input to the semiconductor device. Programmable redundancy is provided by sensing resistance decreases due to dopant redistribution, e.g., in a polysilicon fuse element in a programmable antifuse circuit. This reference does not teach an arrangement of antifuses in vertically stacked relation and sharing a common intermediate electrode therebetween in the manner of the present invention.
It is desirable to have an area efficient arrangement of antifuses in vertically stacked, e.g., aligned, relation and sharing a common intermediate electrode therebetween, without an area penalty, so as to increase semiconductor wafer yield and reduce costs, and especially to have a combination of different type antifuses in such arrangement, preferably with redundancy of one or more of such types of antifuses, without compromising maximum pitch reduction between laterally adjacent antifuses.